Serial RapidIO PCI Bridge

The Serial RapidIO PCI Bridge provides the capability to bridge between Serial RapidIO and PCI. It is part of a family of bridge devices aimed at applications wishing to take advantage of the Serial RapidIO interconnect.

Serial RapidIO is a switched data communication standard developed for the interconnection of devices on the same circuit board or between circuit boards across a backplane at rates in excess of 10Gbps. It has been developed as a more cost-effective, standards based replacement for expensive proprietary busses in high-performance embedded systems, such as networking and communications equipment and enterprise storage.

Cost pressures and the availability of a large base of standard components such as IO Controllers and processing elements has meant that many of the devices and sub-systems utilized in today’s embedded systems have been sourced from the PCI dominated Commercial Computer market. By allowing both technologies to easily co-exist, the Serial RapidIO PCI Bridge allows developers of RapidIO based systems a route to still capitalise on this rich base of cost effective PCI based products, whilst also providing a simple migration path to Serial RapidIO for existing PCI based sub-systems.

Using a series of PCI address mapped windows, the Serial RapidIO PCI Bridge converts PCI memory reads and writes seamlessly into RapidIO transactions. Each window may be configured to translate to RapidIO IO or Maintenance transactions and to a different RapidIO destination. Received RapidIO IO transactions are translated into PCI memory accesses using an integrated DMA controller.

Block Diagram

Features

Provides a fully transparent bridge between

• 1x/4x Serial RapidIO Interface (Rev 1.3)
•  32-bit @ 66MHz PCI (Version 2.2) Interface

RapidIO Serial Physical Layer Features

• Operating rates of 1.25 or 2.5Gbaud per lane
• Operates in either 1x or 4x mode
• Processing and generation of all physical-layer packet overhead
  • Control symbols for Link Initialisation, Transmission and Maintenance
  • Link error detection and recovery
  • Physical Layer Flow Control
  • Generation and processing of Multicast and Reset events
• Support for up to 16 in-flight packets on the physical link
•  Automatic packet retransmission
• Priority reordering of transmit packets using separate priority queues
• Programmable time-out counters
• Implementation defined error reporting based on error management extensions

RapidIO Transport and Logical Layer Features

• Supports the following RapidIO transactions
  • NREAD
  • NWRITE
  • NWRITE_R
  • SWRITE
  • RESPONSE
  • MAINTENANCE
• Support for 8-bit and 16-bit device ID’s
• 34-bit offset addressing
• Ability to handle all legal sizes of RapidIO transactions
• Support for up to 8 outstanding logicallayer transactions
• Automatic RESPONSE generation
• RESPONSE time-out counters
• Automatic mapping between PCI Memory accesses and RapidIO IO or Maintenance transactions

PCI Interface Features

• 32-bit @ 66MHz PCI (2.2) Interface
• PCI Initiator and Target functionality
• Supports PCI Configuration and Memory Read and Write commands
• Eight 2MB PCI Host windows
• Supports up to four simultaneous PCI reads
• Single PCI interrupt request output

Implementation

• Altera Startix II GX -EP2SGX30-C5
  • 780 pin BGA package
• Available in other FPGA technologies

Benefits

• Reduced host processor and software overhead
• Integrated Serdes
• Interoperabity tested against 3rd party devices including Freescale’s PowerQUICCIII, Tundra Semiconductor's Tsi568A Switch, and Altera's Serial RapidIO Physical Interface