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The Reed Solomon Forward Error Correction (RSFEC) Codec provides the necessary functionality to enable FEC encoding and decoding in a single core. The high performance architecture of the core results in a low latency and low gate count implementation, enabling low power, scaleable solutions for data rates up to and in excess of 40Gbps. The core is adaptable to fit a wide range of applications, such as Digital Wrapper and SONET framers. Block Diagram |
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