Serial RapidIO to AHB Interface IP Cores

Jennic's Serial RapidIO system-level IP product line provides a complete range of fully integrated Serial RapidIO interface solutions, intended for integration into SoC semiconductor devices. Serial RapidIO is a data communication standard provisioned for the interconnection of devices on the same circuit board or between circuit boards across a backplane. It has been developed as a more cost-effective, standards, switched based replacement for expensive proprietary busses in high-performance embedded systems, such as networking and communications equipment and enterprise storage.

Jennic's RapidIO product line is based around a generic, modular architecture from which a variety of solutions can be easily created to effectively and efficiently address customers’ specific requirements. The architecture has been partitioned in such a way to support the use of customers own IP, or that of 3rd party IP providers, such as IO cells and SerDes.

The Serial RapidIO to AHB Interface IP cores have been developed specifically for customers wanting to add Serial RapidIO capability to their SoC designs that utilize an on-chip AMBA bus. They have been optimized for implementation in a variety of technologies, including FPGA, Structured ASIC and Cell Based ASIC.

Block Diagram

Features

• Conforms to the RapidIO Interconnect Specification – Rev.1.3.
• Serial RapidIO interface capable of supporting full duplex data rates up to 10Gbps in each direction
• Serial RapidIO Interface
  • Utilises ASIC vendors PHY technology
• Operates at 1.25, 2.5 or 3.125Gbaud per lane
• Supports 4x and 1x operation
• Two Cores Available
  • Serial RapidIO to AHB Interface (Transparent)
  • Serial RapidIO to AHB Interface (Queue)
• Serial RapidIO to AHB Interface (Transparent)
  • Provides an efficient RapidIO interface for low bandwidth/control type applications
  • Uses host bus snooping to provide a transparent interface suitable for use in bridging applications
  • Support Input/Output NREAD, NWRITE, NWRITE_R, SWRITE and Maintenance transactions
• Serial RapidIO to AHB Interface (Queue)
  • Provides a RapidIO interface for higher bandwidth/control and data applications
  • Contains enhanced DMA engines to transfer data using queue memory structures to reduce overhead on host processor
  • Supports NREAD, NWRITE, NWRITE_R, SWRITE, MESSAGE, DOORBELL, Port Writes and Maintenance transactions
• AHB Interface
  • Compliant to AMBA Standard Rev2.2
  • 32bit @ up to 300MHz

Benefits

• Provided as a fully integrated solution requiring no optimisation or customisation by the user.
• Based on Jennic's silicon proven IP, verified against devices including
  • Freescale's PowerQUICCIII
  • Tundra Semiconductor's Tsi568A switch
  • Altera's Serial RapidIO Physical Interface
• Passed ASIC vendors IP compliance checklist to ensure ease of integration into users design.
• Available through the following IP Partner Programs including
  • LSI Logics RapidChip
  • NEC-Electronics OAP

Options

• Support for Error Management and Flow Control Extensions.
• 1x lane only Serial Physical Interface
• Optimised version available in FPGA for evaluation purposes