ATM SAR for DSLAM products

Jennic’s SAR-DSLAM provides a high capacity implementation of an ATM segmentation and re-assembly function for Central office DSL Access Multiplexor (DSLAM) applications. The SAR-DSLAM is implemented as a pre-configured hardware module, to enable rapid development of highly integrated System-on-Chip products for the high end DSLAM market.

The SAR-DSLAM features an extended UTOPIA-2 master interface for connection to up to 96 DSL modems or a UTOPIA-2 slave mode enabling direct connection to an ATM switch fabric. The non-blocking architecture ensures maximum network performance. The hardware accelerator based architecture minimises the processing load and system power required to support ATM on a high throughput network link maximising the number of subscriber lines that can be supported. The SAR-DSLAM will operate at full-duplex data rates of up to 622Mbps on a system clock speed as low as 100MHz. It can support AAL5 and AAL0 for all PDU types at full line-rate, with ‘per VC’ priority and traffic shaping for CBR, VBR and UBR service classes.

The J-SAR-DSLAM is an implementation of Jennic’s Modular SAR product family, a range of highly configurable hardware ATM segmentation and re-assembly engines, which operate at full-duplex data rates of up to 622Mbps. The SAR architecture includes support for real-time data interfaces which bypass the host processor, for delivery of real-time data e.g. voice and video. These are mapped to ATM using the AAL2 and AAL1 protocol processors.

Block Diagram