ATM SAR for 3G Basestations

Jennic’s SAR-3G provides a high capacity implementation of an ATM segmentation and re-assembly function for 3G telecom network basestation applications. The SAR-3G supports both AAL2 and AAL-5 for efficient simultaneous transport of both voice and data. The SAR-3G is implemented as a pre-configured hardware module, to enable rapid development of highly integrated System-on-Chip products for the rapidly developing 3G market.

The SAR-3G will operate at full-duplex data rates of up to 622Mbps on a system clock speed as low as 100MHz. It can support AAL2, AAL5 and AAL0 for all PDU types at full line-rate, with ‘per VC’ priority and traffic shaping for CBR, VBR and UBR service classes. The SAR-3G supports up to 1024 virtual connections with up to 255 channels on each VC. The hardware accelerator based architecture minimises the processing load and system power required to support ATM on a high throughput network link maximising the number of subscriber lines that can be supported.

The J-SAR-3G is an implementation of Jennic’s Modular SAR product family, a range of highly configurable hardware ATM segmentation and re-assembly engines, which operate at full-duplex data rates of up to 622Mbps. The SAR architecture includes support for real-time data interfaces which bypass the host processor, for delivery of real-time data e.g. voice and video. These are mapped to ATM using the AAL2 and AAL1 protocol processors.

Block Diagram

Features

• Up to 622Mbps full duplex operation
• Support for 1024 Virtual Circuits
• Supports 255 channels per VC
• PCI, IBM PLB4, AHB Host interface options
• Support for AAL2, AAL5 and AAL0 raw cell
• AAL2 for Voice and Data
• Cell header and AAL-5 trailer generation and termination.
• Traffic shaping for VBR, CBR, or UBR
• Calendar based transmit traffic scheduler
• Traffic parameters assigned on a per-circuit basis
• UTOPIA-2 Master/Slave interface
• Fully synthesisable module
• Architecture supports all PDU types.
• Conforms to ATM-Forum and ITU-T specifications
• Supports ATM signalling, RM, OAM, and ILMI cell flows
• Simultaneous full line-rate transmit and receive processing
• RFC2684 MpoA, RFC 2364 PPPoA
• Non-blocking Architecture Performance Monitoring

Benefits

• Technology independent hardware implementation
• Low power, low silicon area design.
• Flexible high-performance architecture optimised for consumer network access applications.

Options

• Custom configurations are also available