SPI 4.2 Interface Solutions

The SPI-4.2 Interface is a range of IP cores that implement the physical interface and advanced protocol management functions required to provide a variety of SPI-4.2 and NPSI compliant interface solutions. They are intended to be used with a range of Jennic’s IP cores, such as it’s OC-192 SONET Framer, Multi-Protocol Payload Processor and Packet Bridge to create high performance, feature rich devices such as Intelligent Physical Layer Framers.

The SPI-4.2 Physical Interface contains the LVDS IO cells, PLL and the high speed mixed signal circuits to convert the external DDR data and control signals on to the internal on-chip bus and to perform the dynamic de-skew.

The SPI-4.2 Protocol Controller performs encapsulation of packet data and out-of-band packet delineators into a SPI-4.2 datastream, which is then extracted at the receiving end. In the opposite direction, FIFO status information is formed into status frames, where it processed at the receiving end to calculate credit and perform flow control. An additional version of SPI-4.2 Protocol Controller is also available, offering highly configurable channelised FIFOs, arbitrator and automatic status generation to aid system integration.

To provide compliance with the NPSI standard, these cores offer a number of additional features, such as, extended addressing modes, high speed LVDS status interface and enhanced flow control.

Block Diagram

Features

• Conforms to
  • OIF SPI-4 Phase 2 (Jan 2001)
  • Saturn Group POS Phy Level 4
  • Network Processor Streaming Interface
• Fully compatible with a range of Jennic’s IP cores
• Scaleable architecture to support data rates up to 16 Gbps
• Suitable for a wide range of applications
  • Channelised Intelligent Physical Layer Framers
  • Network Processors
  • Traffic Managers
  • Bridge Chips
     

SPI-4.2 Physical Interface

• Hard macro available to customer specific package constraints
• Integrated LVDS IO cells
• Performs dynamic data deskew to compensate for differential clock and data skew of up to +/- 1 data bit
• Integrated high performance PLL to achieve required jitter performance
• Inward and outward facing port loopbacks

SPI-4.2 Protocol Controller

• Support 1 to 256 ports
• Generation and processing of In-band Control Words and Training sequences
• Programmable Maxburst1/2 and data burst size
• Interface and packet protocol error processing, including DIP-4/DIP-2 parity generation and checking with programmable error thresholds
• Status frame generation and processing, including per-port credit calculation
• Programmable calendar parameters
   

SPI-4.2 Protocol Controller (with FIFOs)

• Integrated channelised FIFOs with programmable features per port
  • Data-available watermarks
  • Memory allocation
• Arbitration with programmable weighting factors
• Payout buffers to ensure efficient data throughput when transferring smaller packets
   

NPSI Enhancements

• High speed LVDS status interface
• Extended addressing modes
• Enhanced flow control mechanism